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High Speed Synchronous Power MOSFET Smart Driver
POWER MANAGEMENT Description
The SC1405B is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through. Each driver is capable of driving a 3000pF load in 15ns rise/ fall time and has ULTRA-LOW propagation delay from input transition to the gate of the power FET's. Adaptive Overlap Protection circuit ensures that the synchronous FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning high is externally programmable via a capacitor to minimize dead time. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET's gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output Over-Voltage protection circuitry, independent of the PWM controller. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are off when Vcc is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in standby mode, reducing supply current to less than 10A. SC1405B is offered in a high pitch (.025" lead spacing) TSSOP package.
SC1405B
Features
Fast rise and fall times (15ns with 3000pf load) 14ns max. Propagation delay (BG going low) Adaptive and programmable shoot-through protection Wide input voltage range (4.5-25V) Power saving asynchronous mode control Output overvoltage protection/overtemp shutdown Under-Voltage lock-out and power ready signal Less than 10A stand-by current (EN=low) Improved drive version of SC1405TS High frequency (to 1.2MHz) operation allows use of small inductors and low cost capacitors in place of electrolytics
Applications
High Density/Fast transient microprocessor power supplies Motor Drives/Class-D amps High efficiency portable computers
Typical Application Circuit
INPUT POWER, 5-20V + Vcc 10uF,6.3V + .1uF 8 3 << >> P_READY PWM IN (20KHz-1MHz) 47pF 7 2 4 6 1 5 14 13 12 SC1405 9 11 10 2.2 2.2 MTB75N03 75A,30V 5817 .22uF 1.7V@30A + + + + + MTB75N03 75A,30V
<< DSPS_DR
Over-Voltage Sense
<<< Output Feedback to PWM Controller
Revision: January 13, 2004
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SC1405B
POWER MANAGEMENT Absolute Maximum Ratings
Parameter VCC Supply Voltage BST to PGND BST to DRN DRN to PGND DRN to PGND Pulse OVP_S to PGND Input Pin Continuous Power Dissipation Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. Symbol VMAXSV VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXPULSE VMAXOVP SPGND CO Pd J C J A TJ TSTG TLEAD TAMB = 25C, TJ = 125C TCASE = 25C, TJ = 125C tPULSE < 100ns Conditions Maximum 7 30 8 -2 to 25 -5 to 25 10 -0.3 to 8.3 0.66 2.56 40 150 0 to +125 -65 to +150 300 Units V V V V V V V W C/W C/W C C C
NOTE: (1) Specification refers to application circuit in Figure 1.
Electrical Characteristics - DC Operating Specifications
Unless specified: -0 < J < 125C; VCC = 6V; 4V < VBST < 26V
Parameter Pow er Supply Supply Voltage Quiescent Current Quiescent Current, operating PR D Y High Level Output Voltage Low Level Output Voltage Sink Current
Symbol
Conditions
Min
Typ
Max
Units
V CC Iq_stby Iq_op E N = 0V VCC = 5V, CO = 0V
4.15
5
6.0 10
V A mA
1
VOH VOL IO_SINK
VCC = 4.6V, lload = 10mA VCC < UVLO threshold, lload = 10A VPRDY = 0.4V
4.5
4.55 0.1 0.2
V V mA
5
10
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SC1405B
POWER MANAGEMENT Electrical Characteristics - DC Operating Specifications
Parameter D S P S _D R High Level Output Voltage Low Level Output Voltage Under Voltage Lockout Start Threshold Hysteresis Logic Active Threshold Overvoltage Protection Trip Threshold Hysteresis S_MOD High Level Input Voltage Low Level Input Voltage Enable High Level Input Voltage Low Level Input Voltage CO High Level Input Voltage Low Level Input Voltage Thermal Shutdow n Over Temperature Trip Point Hysteresis High-Side Driver Peak Output Current Output Resistance IPKH RsrcTG RsinkTG Low -Side Drive Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100s, TJ = 125C, VV S = 4.6V, VBG = 4V (src) or VLOWDR = 0.5V (sink) 3 1.2 duty cycle < 2%, tpw < 100s, TJ = 125C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN 3 1 .7 TOTP THYST 165 10
o o
Symbol
Conditions
Min
Typ
Max
Units
VOH VOL VSTART VhysUVLO V AC T VTRIP VhysOVP VIH VIL VIH VIL VIH VIL
VCC = 4.6V, Cload = 100pF VCC = 4.6V, Cload = 100pF
4.15 0.05 4.2 4.4 0.05 1.5 1.145 1.2 0.8 2.0 0.8 1.255 4.6
V V V V V V V V V
2.0 0.8
V V
2.0 0.8
V V C C
A
A
1.0
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SC1405B
POWER MANAGEMENT Electrical Characteristics - AC Operating Specifications
Parameter High Side Driver rise time fall time propagation delay time, TG going high propagation delay time, TG going low Low -Side Driver rise time fall time propagation delay time, BG going high propagation delay time, TG going low Under-Voltage Lockout V_5 ramping up V_5 ramping down PR D Y EN is transitioning from low to high tpdhPRDY V_5 >UVLO threshold, Delay measured from EN > 2.0V to PRDY > 3.5V V_5 >UVLO threshold, Delay measured from EN < 0.8V to PRDY < 10% of V_5V 10 s tpdhUVLO tpdhUVLO EN is High EN is High 10 10 us us trBG trBG tpdhBGHI tpdlBG CI = 3nF, V CI = 3nF, V
VS VS
Symbol
Conditions
Min
Typ
Max
Units
trTG1 tfTG tpdhTG tpdlTG
CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 CI = 3nF, VBST - VDRN = 4.6V,
14 12 20 15
23 19 32 24
ns ns ns ns
= 4.6V, = 4.6V,
15 13 12 7
24 21 19 12
ns ns ns ns
CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 CI = 3nF, V V S = 4.6V, DRN <1V
EN is transitioning fro high to low D S P S _D R rise/fall time propagation delay, DSPS_DR going high propagation delay, DSPS_DR goes low Overvoltage Protection propagation delay
tpdhUVLO
500
s
trDSPS DR. tpdhDSPS DR tpdlDSPS DR
CI = 100 pf, V_5 = 4.6V S_MOD goes high and BG goes high or S_MOD goes low S_MOD goes high and BG goes low
20 10 10
ns ns ns
tpdhOVP S
V_5 + 4.6V, TJ = 125OC, OVP_S > 1.2V to BG > 90% of V _5
1
s
Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1405B
POWER MANAGEMENT Timing Diagrams
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SC1405B
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device
(1)
P ackag e TSSOP-14
Temp Range (TJ) 0 to 125C
SC1405BTS.TR
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
(14-Pin TSSOP)
Pin Descriptions
Pin # 1 2 3 4 5 6 Pin Name OVP_S EN GND CO S_MOD DELAY_C Pin Function Overvoltage protection sense. External scaling resistors required to set protection threshold. When high, this pin enables the internal circuitry of the device. When low, TG, BG, and PRDY are forced low and the supply current (5V) is less than 10A. Logic GND. TTL-level input signal to the MOSFET drivers. When low, this signal forces BG to be low, triggering asynchronous operation. When high, BG is not a function of this signal. The capacitance connected between this pin and GND sets the additional propagation delay for BG going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the propragation delay = 20ns. This pin indicates the status of VCC. When VCC is less than the UVLO threshold, this output is driven low. When VCC is greater than or equals to the UVLO threshold this output goes high. Input supply of 5V - 6V. A .22-1F ceramic capacitor should be connected from VCC to PGND very close to the chip. Output drive for the synchrounous (bottom) MOSFET. Power ground. Connect to the synchronous FET source pin (power ground). Dynamic Set Point Switch Drive. TTL level output signal. When S-MOD is high, this pin follows the BG driver pin voltage. This pin connects to the junction of the switching and synchronous MOSFET's. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic).
7
PRDY
8 9 10 11 12 13 14
VC C BG PGND D S P S _D R DRN TG BST
NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1405B
POWER MANAGEMENT Block Diagram
Applications Information
SC1405B is the higher speed version of the SC1405. It is designed to drive Low Rds_On power MOSFET's with ultra-low rise/fall times and propagation delays. As the switching frequency of PWM controllers is increased to reduce power supply and Class-D amplifier volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOSFET) and reduce Dead-time (BOTTOM MOSFET) losses. While Low Rds_On MOSFET's present a power saving in I2R losses, the MOSFET's die area is larger and thus the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and deadtime losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC1405 family of parts presents a total solution for the high-speed, high power density =applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as ClassD amplifiers. Theory of Operation The control input (CO) to the SC1405B is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence
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of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FET's are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor from the C-Delay pin to GND. The delay is approximately 1ns/pf in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance MOSFET's are used in parallel and the fall time is substantially greater than 20ns. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since the parallel Schottky or the bottom FET body diode will have to conduct during dead-time. Layout Guidelines As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1405B. The Evaluation board schematic (Refer to figure 3) shows a dual phase synchronous design with all surface mountable components.
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SC1405B
POWER MANAGEMENT Applications Information
While components connecting to C-Delay, OVP_S, EN,SMOD, DSPS_DR and PRDY are relatively non-critical, tight placement and short,wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the TOP gate, it must be less than .5" away from the SC1405. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than .5" away from the SC1405. The ground node of this capacitor, the SC1405 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land and multiple vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS Drain and source. Any trace or lead inductance in these connections will drive current way from the Shottkey and allow it to flow through the FET's Body diode, thus reducing efficiency. Preventing Inadvertent Bottom FET Turn-on At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET's gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is:
VSPIKE = VIN * CRSS (CRSS + CISS
MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOSFET shown in the schematic (figure 4) has a 2 volt threshold and will require approximately 5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. Ringing on the Phase Node The top MOSFET source must be close to the bottom MOSFET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by:
FRING = 1 (2 * (L ST * COSS
Where:
Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET's source and the bottom FET's drain added to the trace resistance of the bottom FET's ground connection. Coss=Drain to source capacitance of bottom FET. If there is a Shottkey used, the capacitance of the Shottkey is added to the value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. This ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1405 should eliminate the double pulsing. The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. If the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device's absolute maximum rating of 8V.
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Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405B is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate if rise of current,etc. While not shown in Figure 4, a capacitor may be added from the gate of the Bottom FET to its source, preferably less than .5" away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The selection of the bottom MOSFET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also
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SC1405B
POWER MANAGEMENT Applications Information (Cont.)
To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount MOSFETs will reduce lead inductance and their parasitic effects. ASYNCHRONOUS OPERATION The SC1405B can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling the bottom FET drive. This has the effect of saving power at light loads since the bottom FET's gate capacitance does not have to charged at the switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is less than 1/2 inductor ripple current. At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant. Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. DC regulation can be an issue when operating in asynchronous mode, depending on the type of controller used and minimum load required to maintain regulation. If there are no Shottkey diodes used in parallel with bottom FET, the FET's body diode will need to conduct in asynchronous mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of operation. DSPS DR This pin produces an output which is a logical duplicate of the bottom FET's gate drive, if S-MOD is held LOW. OVP_S/OVER TEMP SHUTDOWN Output over-voltage protection may be implemented on the SC1405 independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to allow discharge of the output capacitors excessive voltage through the output inductor. There should be sufficient RC time constant as well as voltage headroom on the OVP_S pin to assure it does not enter overvoltage mode inadvertently. The SC1405 will shutdown if its Tj exceeds 165C.
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SC1405B
POWER MANAGEMENT Typical Characteristics
Performance diagrams, Application Evaluation Board.
PIN Descriptions
Figure 1: PWM input and Gate drive switching waveforms. The MOSFETs driven are shown on Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
Figure 2: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are shown on Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
Figure 3: PWM input and Gate drive and phase node switching waveforms with time scale expanded. The MOSFETs driven are shown on Figure 4 (Evaluation Board Schematic) Ch1: PWM input signal Ch2: Top Gate Drive Ch3: Phase (Switching) Node Ch4: Bottom Gate
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1u,16V
6 5 4 3 2 1 R2 10 10nf 1uf C12 C11 FDB 6035 BS T TG 12 FDB 7030 9 R6 0 Q2 10u,CE R C17 R7 2.2 VIN FDB 6035 0 Q3 L2 13 12 FDB 7030 9 2.2 R13 0 11 10 Q4 .01 C27 10u,CE R C28 R19 7.5K C30 .1 R17 1 R18 7.5K 10u,CE R C29 10u,CE R C25 R12 10u,CE R C23 10u,CE R C22 .1 C20 PIT1103 _1uh 11 10 L1 C16 .01 10u,CE R C15 13 R5 0 PIT1103 _1uh 14 Q1 .1 C14 U? 10uf R4 1 VID4 VCC BGOUT OC+ 5 13 12 D4 5819 R9 BS T TG 14 U3 8 3 Vcc GND R20 3.6K SC2422-P R14 13K C26 SC1 405B 10nf 5 SC1 405B OUT1 OUT2 OC7.5K 7 FB UVLO GND 9 RRE F 8 10 C21 11 R8 10uf 14 15 2 VID3 VID2 VID1 VID0 ERROUT 3 4 5 16 10k Vcc GND 8 3 5819 U1 C9 10 R3 1uf 10u,CE R 10u,CE R 1uf
C7
C8
1000uf,16V
APPLICATION EVAL ALU BOARD SCHEMATIC Figure 4 - APPLICATION EVAL U ATION BO ARD SCHEMATIC
All VIDs OFF disables the SC2422 Controller.
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R1 C3 .002 C4 C5 C6
5-7V Vin
J1
+12V
10u,CE R C1
33u f,OS C2
POWER MANAGEMENT Evaluation Board Schematic
Vcc
D2
820u f,OS C10
INPUT
Vid4 EN
PRDY DRN EN CO DELA Y_ C BG OVP_S DSPS_DR S_MO D PGND 7 2 4 6 1
820u f,OS C13
Vid3
Vid2
Vid1 Vcc
Vid0
6
10u,CE R C18 10u,CE R C19
11
7 2 4 6 1 PRDY EN DRN CO DELA Y_ C BG OVP_S DSPS_DR S_MO D PGND
R10
R11
120K
1K
220pf
C24
R15
26.1k
R16
OVP
7.5K
VCORE
SC1405B
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SC1405B
POWER MANAGEMENT Evaluation Board Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Qty. 12 1 3 1 1 2 2 2 3 2 1 2 1 2 2 2 1 2 1 4 2 4 1 1 1 1 1 1 1 2 Reference C 1, C 4, C 5, C 15, C 17, C 18, C 19, C 22, C 23, C 25, C 28, C 29 C2 C3, C6, C11 C7 C8 C 9, C 26 C 10, C 13 C 21, C 12 C 14, C 20, C 30 C 16, C 27 C 24 D 4, D 2 J1 L2, L1 Q1, Q3 Q2, Q4 R1 R3, R2 R4 R5, R6, R9, R13 R12, R7 R8, R16, R18, R19 R10 R11 R14 R15 R17 R20 U2 U1, U3
12
Value 01u, Cer. 33uf, OS 1uF 1u, 16V 1000uf, 16V 10nf 820uf, OS 10uf .1 .01 220pf 5819 INPUT PIT1103_luh F D B 6035 F D B 7030 .002 10 10k 0 2.2 7.5K 120K 1K 13K 26.1k 1 3.6K S C 2422 S C 1405B
Manufacturer Murata, TDK Sanyo
Panasonic
Sanyo
Falco (Falcousa.com) Fairchild Fairchild Dale
Semtech Semtech
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2004 Semtech Corp.
SC1405B
POWER MANAGEMENT Outline Drawing -TSSOP-14
Land Pattern - TSSOP-14
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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